1. Field of the Invention
The embodiments of the invention relate to circuit design, and, more specifically, to design of an electronic circuit. Although embodiments of the invention are suitable for a wide scope of applications, it is particularly suitable for the concurrent design of electronic modules across different design entry tools targeted to a single simulation netlist.
2. Discussion of the Related Art
In general, an electronic circuit includes many electronic components and modules (e.g. antennae, transistors, diodes, inductors, capacitors, inverters, logic gates, multiplexers, integrated circuit (IC) chips, field programmable gate arrays (FPGAs) for performing various electronic functions. Each component or module is interconnected in a prescribed manner to respond to input electrical signals and produce other electrical signals according to the desired electronic function performed by the circuit. Some modules, such as ICs, system in a package (SiPs), and printed circuit boards (PCBs), may consist themselves of various interconnected modules or components.
The modules of a circuit are frequently designed by different teams, each team having a specific expertise. Each team will use tools specialized for design in its area, such as a spreadsheet design environment for large pin-count devices like processors and field-programmable gate arrays or a schematic design environment for analog and radio frequency (RF) modules. Each team may have design considerations unique to that team, but the modules should ultimately work together in the circuit layout which meets the requirements of all modules. For example, the layout of analog portions of the circuit is typically guided by considerations including trace thickness, trace separation, and ground loops. The layout of RF portions of circuits is typically guided by considerations of trace shapes, route contours, and metal structures for passives. In contrast, the layout of digital portions of circuits is typically guided by bus routing considerations and signal integrity constraints including route schedules and topologies. The final layout should ensure that various constraints of the circuit are met, such as that the router meets routing schedules and the RF portion meets RF shape routing criteria. However, there is tension between the desire for different teams to work independently and concurrently upon the design of modules of the circuit and the need to satisfy global constraints.
There are several methods for concurrent and independent design and simulation of modules according to the related art. In one method, known as reuse module flow, one team creates a reuse module using that team's preferred design entry tool. Another team imports this module into its own design entry tool as a hierarchical block. However, any change to a reuse module requires complete replacement of the hierarchical block, and therefore constant resynchronization amongst the teams counteracts concurrent and independent work. To allow simulation using reuse modules, netlists must be exchanged in advance across design entry tools, and components of the reuse module must be completely laid out in a separate session before importation into the master layout unless the designer chooses to flatten the modules.
In another related art method for concurrent and independent design and simulation of modules, the layout is physically partitioned in advance for purposes of satisfying global constraints by a separate tool, which is also used for simulation. However, the partitioning and simulation are not driven by the design entry tools used to independently create the layout of the modules. Thus, there is no capability to impose different rule sets for the different partitions during simulation or design.
Mixed signal (IC) flow is another method used for concurrent and independent design and simulation of modules involving an analog portion and a digital portion. Mixed signal IC flow allows separate digital and analog teams to independently work on floor-plan and layout of separate analog and digital ICs, which are later merged onto a single layout. However, the two separate teams are creating separate layouts rather than creating pieces of the same layout, and the layouts are merged after the designing process is complete, rather than merging data at the time of writing to the layout by the design entry tool. In addition, the relationship between the digital and analog section can not be fully modeled by the design entry tools; instead the relationships are defined in verilog which goes into register transfer level (RTL) synthesis to Encounter, much like a reuse flow instead of capturing the full relationship. Another limitation of mixed signal IC flow is that simulation can not be performed across the design entry tools of the two teams. A further limitation to mixed signal IC flow is that it is not applicable to printed circuit boards or systems in packages design flows.
Piecemeal simulation is still another method for concurrent and independent design and simulation of modules. In piecemeal simulation, portions of design created across different design entry tools are manually captured and imported into a design entry tool. Such an approach is limited by the necessity to manually stitch the netlists across the different design entry tools and the tools used to generate the objects captured for importation. Simulation netlists created by piecemeal simulation can not be linked to the final layout.